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01711cam a2200313 a 4500 |
| 001 |
c000225874 |
| 003 |
CARM |
| 005 |
20061124144519.0 |
| 008 |
990105s1999 maua b 001 0 eng |
| 010 |
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|a 99011572
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| 019 |
1 |
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|a 14454387
|5 LACONCORD2021
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| 020 |
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|a 0792384563 (alk. paper)
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| 035 |
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|a (OCoLC)40602898
|5 LACONCORD2021
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| 040 |
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|a TOC
|b eng
|c TOC
|d TOC
|
| 042 |
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|a pcc
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| 050 |
0 |
0 |
|a TK7868.L6
|b S26 1999
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| 082 |
0 |
0 |
|a 621.39/5
|2 21
|
| 100 |
1 |
|
|a Sasao, Tsutomu,
|d 1950-
|
| 245 |
1 |
0 |
|a Switching theory for logic synthesis /
|c Tsutomu Sasao.
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| 260 |
|
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|a Boston, Mass. :
|b Kluwer Academic Publishers,
|c 1999.
|
| 300 |
|
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|a viii, 362 p. :
|b ill. ;
|c 24 cm.
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| 504 |
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|a Includes bibliographical references (p. [331]-353) and index.
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| 505 |
0 |
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|a 1. Mathematical Foundation -- 2. Lattice and Boolean Algebra -- 3. Logic Functions and their Representations -- 4. Optimization of and-or-Two-Level Logic Networks -- 5. Logic Functions with Various Properties -- 6. Sequential Networks -- 7. Optimization of Sequential Networks -- 8. Delay and Asynchronous Behavior -- 9. Multi-Valued Input Two-Valued Output Function -- 10. Heuristic Optimization of Two-Level Networks -- 11. Multi-Level Logic Synthesis -- 12. Logic Design Using Modules -- 13. Logic Design using Exors -- 14. Complexity of Logic Networks -- A. History of Switching Theory.
|
| 650 |
|
0 |
|a Logic design
|x Data processing.
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| 650 |
|
0 |
|a Sequential machine theory.
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| 650 |
|
0 |
|a Switching theory.
|
| 852 |
8 |
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|b CARM
|h A2:AE08H0
|i C08720
|p 0340003
|f BK
|
| 999 |
f |
f |
|i 6de04a09-4ff8-5514-8ce1-a6236badcfb3
|s d35c0278-688f-5270-9681-3fcd5e4d4f3f
|
| 952 |
f |
f |
|p Can circulate
|a CAVAL
|b CAVAL
|c CAVAL
|d CARM 1 Store
|e C08720
|f A2:AE08H0
|h Other scheme
|i book
|m 0340003
|