Formal VLSI correctness verification : proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design /

Formal VLSI correctness verification : proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design /

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Bibliographic Details
Corporate Authors: IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design Houthalen, Belgium, Interuniversity Micro-Electronics Center
Other Authors: Claesen, Luc J. M.
Format: Conference Proceeding Book
Language:English
Published: Amsterdam ; New York : New York, N.Y. : North-Holland ; Distributed in the U.S. and Canada, Elsevier Science Pub. Co., 1990.
Series:VLSI design methods ; 2
Subjects:
Integrated circuits > Very large scale integration > Design and construction > Data processing > Congresses.
Computer-aided design > Congresses.
Integrated circuits > Verification > Congresses.
Description
Physical Description:xv, 427 p. : ill. ; 23 cm.
Bibliography:Includes bibliographical references.
ISBN:0444886885 (U.S.)

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